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Discussione: POST CODE 59 HV_0x59_S_INIT_SOC_MMIO

  1. #1
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    POST CODE 59 HV_0x59_S_INIT_SOC_MMIO

    Buondi,qualcuno conosce a cosa si riferisce il POST CODE HV_0x59_S_INIT_SOC_MMIO ?

    Nand originale,CB 5773,kernel 14719,falcon






    Questa la sequenza dei post code


    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    1C 1BL_0x1C_S_SHA_COMPUTE
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1C 1BL_0x1C_S_SHA_COMPUTE
    59 HV_0x59_S_INIT_SOC_MMIO
    FD
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1C 1BL_0x1C_S_SHA_COMPUTE
    59 HV_0x59_S_INIT_SOC_MMIO
    FD
    C0
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1C 1BL_0x1C_S_SHA_COMPUTE
    59 HV_0x59_S_INIT_SOC_MMIO
    FD
    0


    grazie
    Ultima modifica di marchisio80; 15-10-2015 alle 17:28

  2. #2
    Moderatore L'avatar di DrSchottky
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    Quella post sequence sballata, scommetto che non fai lo shift dei livelli logici prima di entrare sul JRP/slave.
    O provvedi ad adeguare le tensioni o misura il postcode con tester quando va in RROD.

  3. Thanks marchisio80 Ha ringraziato per questo post
  4. #3
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    NN saprei,il post sniffer me lo avevano costruito,ma non lo uso da tanto,e' attaccato a sta falcon da anni,magari non funziona piu' perfettamente xD

    era una CB 5772 in origine,se nn ricordo male E64 ai tempi
    come programma per leggere i post code sto usando Post Sniffer.exe

    Purtroppo x un po' nn sn a casa,niente tester qui

    ho messo xell(RGH2) e si avvia correttamente,la sequenza e' questa,non e' corretta?

    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1C 1BL_0x1C_S_SHA_COMPUTE
    D0 2BLL_0xD0_S_BEGIN
    D1 2BLL_0xD1_S_READ_FUSES
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    DC
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    20 2BL_0x20_S_BEGIN
    0
    20 2BL_0x20_S_BEGIN
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    15 1BL_0x15_S_FETCH_OFFSET
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1C 1BL_0x1C_S_SHA_COMPUTE
    D0 2BLL_0xD0_S_BEGIN
    D1 2BLL_0xD1_S_READ_FUSES
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    DC
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    F0 2BLL_0xF0_E_VERIFY_OFFSET_CB_B
    0
    C0
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    15 1BL_0x15_S_FETCH_OFFSET
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1C 1BL_0x1C_S_SHA_COMPUTE
    D0 2BLL_0xD0_S_BEGIN
    D1 2BLL_0xD1_S_READ_FUSES
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    20 2BL_0x20_S_BEGIN
    2D 2BL_0x2D_S_SIG_VERIFY_3BL_CC
    2C 2BL_0x2C_S_SHA_COMPUTE_3BL_CC
    31 2BL_0x31_S_FETCH_HEADER_4BL_CD
    34 2BL_0x34_S_HMACSHA_COMPUTE_4BL_CD
    35 2BL_0x35_S_RC4_INITIALIZE_4BL_CD
    39 2BL_0x39_S_SHA_VERIFY_4BL_CD
    38 2BL_0x38_S_SIG_VERIFY_4BL_CD
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    10
    Ultima modifica di marchisio80; 15-10-2015 alle 18:39

  5. #4
    Moderatore L'avatar di DrSchottky
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    La sequenza non totalmente corretta, nel senso che c' un sacco di garbage e di post mancanti.
    Immagino che tu stia usando il Post logger di Tydye81(che non precissimo). Hai messo in comune le masse, vero?

    La nand originale integra? Visto che xell parte prova a ricrearne una pulita.

  6. Thanks marchisio80 Ha ringraziato per questo post
  7. #5
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    Si,il post logger di Tydye81

    Ora mi sembra abbastanza a posto il post sniffer,dalla sequenza dei post code.


    xell si avvia correttamente e si vede a video


    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE
    13 1BL_0x13_S_FSB_CONFIG_TX_STATE
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    16 1BL_0x16_S_FETCH_HEADER
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1A 1BL_0x1A_S_RC4_INITIALIZE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1E 1BL_0x1E_S_BRANCH
    D0 2BLL_0xD0_S_BEGIN
    D1 2BLL_0xD1_S_READ_FUSES
    D2 2BLL_0xD2_S_VERIFY_OFFSET_CB_B
    D3 2BLL_0xD3_S_FETCH_HEADER_CB_B
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D6 2BLL_0xD6_S_HMACSHA_COMPUTE_CB_B
    D7 2BLL_0xD7_S_RC4_INITIALIZE_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    DA 2BLL_0xDA_S_SHA_VERIFY_CB_B
    DB 2BLL_0xDB_S_BRANCH_CB_B
    20 2BL_0x20_S_BEGIN
    21 2BL_0x21_S_INIT_SECOTP
    22 2BL_0x22_S_INIT_SECENG
    2F 2BL_0x2F_S_RELOCATE
    2E 2BL_0x2E_S_HWINIT
    31 2BL_0x31_S_FETCH_HEADER_4BL_CD
    33 2BL_0x33_S_FETCH_CONTENTS_4BL_CD
    34 2BL_0x34_S_HMACSHA_COMPUTE_4BL_CD
    35 2BL_0x35_S_RC4_INITIALIZE_4BL_CD
    36 2BL_0x36_S_RC4_DECRYPT_4BL_CD
    37 2BL_0x37_S_SHA_COMPUTE_4BL_CD
    3B 2BL_0x3B_S_PCI_INIT
    3A 2BL_0x3A_S_BRANCH
    40 4BL_0x40_S_BEGIN
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE



    freeboot a schermo nn si vede nulla,si ferma al post code 6F KE_S_0x6F_INIT_POWER_MODE


    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE
    13 1BL_0x13_S_FSB_CONFIG_TX_STATE
    17 1BL_0x17_S_VERIFY_HEADER
    15 1BL_0x15_S_FETCH_OFFSET
    16 1BL_0x16_S_FETCH_HEADER
    17 1BL_0x17_S_VERIFY_HEADER
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1A 1BL_0x1A_S_RC4_INITIALIZE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1E 1BL_0x1E_S_BRANCH
    D0 2BLL_0xD0_S_BEGIN
    D1 2BLL_0xD1_S_READ_FUSES
    D2 2BLL_0xD2_S_VERIFY_OFFSET_CB_B
    D3 2BLL_0xD3_S_FETCH_HEADER_CB_B
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D6 2BLL_0xD6_S_HMACSHA_COMPUTE_CB_B
    D7 2BLL_0xD7_S_RC4_INITIALIZE_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    DA 2BLL_0xDA_S_SHA_VERIFY_CB_B
    F2 2BLL_0xF2_E_SHA_VERIFY_CB_B
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE
    13 1BL_0x13_S_FSB_CONFIG_TX_STATE
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    16 1BL_0x16_S_FETCH_HEADER
    17 1BL_0x17_S_VERIFY_HEADER
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1A 1BL_0x1A_S_RC4_INITIALIZE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1E 1BL_0x1E_S_BRANCH
    DE
    D0 2BLL_0xD0_S_BEGIN
    D1 2BLL_0xD1_S_READ_FUSES
    D3 2BLL_0xD3_S_FETCH_HEADER_CB_B
    D6 2BLL_0xD6_S_HMACSHA_COMPUTE_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D6 2BLL_0xD6_S_HMACSHA_COMPUTE_CB_B
    D7 2BLL_0xD7_S_RC4_INITIALIZE_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    DA 2BLL_0xDA_S_SHA_VERIFY_CB_B
    DB 2BLL_0xDB_S_BRANCH_CB_B
    20 2BL_0x20_S_BEGIN
    21 2BL_0x21_S_INIT_SECOTP
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE
    13 1BL_0x13_S_FSB_CONFIG_TX_STATE
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    16 1BL_0x16_S_FETCH_HEADER
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1A 1BL_0x1A_S_RC4_INITIALIZE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1E 1BL_0x1E_S_BRANCH
    D0 2BLL_0xD0_S_BEGIN
    D1 2BLL_0xD1_S_READ_FUSES
    D2 2BLL_0xD2_S_VERIFY_OFFSET_CB_B
    D3 2BLL_0xD3_S_FETCH_HEADER_CB_B
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D6 2BLL_0xD6_S_HMACSHA_COMPUTE_CB_B
    D7 2BLL_0xD7_S_RC4_INITIALIZE_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    DA 2BLL_0xDA_S_SHA_VERIFY_CB_B
    DB 2BLL_0xDB_S_BRANCH_CB_B
    20 2BL_0x20_S_BEGIN
    21 2BL_0x21_S_INIT_SECOTP
    0
    1A 1BL_0x1A_S_RC4_INITIALIZE
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE
    13 1BL_0x13_S_FSB_CONFIG_TX_STATE
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    16 1BL_0x16_S_FETCH_HEADER
    17 1BL_0x17_S_VERIFY_HEADER
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1A 1BL_0x1A_S_RC4_INITIALIZE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1F
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1E 1BL_0x1E_S_BRANCH
    D0 2BLL_0xD0_S_BEGIN
    D1 2BLL_0xD1_S_READ_FUSES
    D2 2BLL_0xD2_S_VERIFY_OFFSET_CB_B
    D3 2BLL_0xD3_S_FETCH_HEADER_CB_B
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D6 2BLL_0xD6_S_HMACSHA_COMPUTE_CB_B
    D7 2BLL_0xD7_S_RC4_INITIALIZE_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    DB 2BLL_0xDB_S_BRANCH_CB_B
    DA 2BLL_0xDA_S_SHA_VERIFY_CB_B
    F2 2BLL_0xF2_E_SHA_VERIFY_CB_B
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE
    13 1BL_0x13_S_FSB_CONFIG_TX_STATE
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    16 1BL_0x16_S_FETCH_HEADER
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1A 1BL_0x1A_S_RC4_INITIALIZE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1E 1BL_0x1E_S_BRANCH
    D0 2BLL_0xD0_S_BEGIN
    D1 2BLL_0xD1_S_READ_FUSES
    D3 2BLL_0xD3_S_FETCH_HEADER_CB_B
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D6 2BLL_0xD6_S_HMACSHA_COMPUTE_CB_B
    D7 2BLL_0xD7_S_RC4_INITIALIZE_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    DA 2BLL_0xDA_S_SHA_VERIFY_CB_B
    DB 2BLL_0xDB_S_BRANCH_CB_B
    20 2BL_0x20_S_BEGIN
    21 2BL_0x21_S_INIT_SECOTP
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE
    13 1BL_0x13_S_FSB_CONFIG_TX_STATE
    15 1BL_0x15_S_FETCH_OFFSET
    16 1BL_0x16_S_FETCH_HEADER
    17 1BL_0x17_S_VERIFY_HEADER
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1A 1BL_0x1A_S_RC4_INITIALIZE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1E 1BL_0x1E_S_BRANCH
    D0 2BLL_0xD0_S_BEGIN
    D1 2BLL_0xD1_S_READ_FUSES
    D2 2BLL_0xD2_S_VERIFY_OFFSET_CB_B
    D3 2BLL_0xD3_S_FETCH_HEADER_CB_B
    D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
    D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
    D6 2BLL_0xD6_S_HMACSHA_COMPUTE_CB_B
    D7 2BLL_0xD7_S_RC4_INITIALIZE_CB_B
    D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
    D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
    DA 2BLL_0xDA_S_SHA_VERIFY_CB_B
    DB 2BLL_0xDB_S_BRANCH_CB_B
    F2 2BLL_0xF2_E_SHA_VERIFY_CB_B
    20 2BL_0x20_S_BEGIN
    21 2BL_0x21_S_INIT_SECOTP
    22 2BL_0x22_S_INIT_SECENG
    2F 2BL_0x2F_S_RELOCATE
    2E 2BL_0x2E_S_HWINIT
    31 2BL_0x31_S_FETCH_HEADER_4BL_CD
    33 2BL_0x33_S_FETCH_CONTENTS_4BL_CD
    34 2BL_0x34_S_HMACSHA_COMPUTE_4BL_CD
    35 2BL_0x35_S_RC4_INITIALIZE_4BL_CD
    36 2BL_0x36_S_RC4_DECRYPT_4BL_CD
    37 2BL_0x37_S_SHA_COMPUTE_4BL_CD
    3B 2BL_0x3B_S_PCI_INIT
    3A 2BL_0x3A_S_BRANCH
    40 4BL_0x40_S_BEGIN
    42 4BL_0x42_S_FETCH_HEADER
    44 4BL_0x44_S_FETCH_CONTENTS
    45 4BL_0x45_S_HMACSHA_COMPUTE
    46 4BL_0x46_S_RC4_INITIALIZE
    47 4BL_0x47_S_RC4_DECRYPT
    48 4BL_0x48_S_SHA_COMPUTE
    4B 4BL_0x4B_S_LZX_EXPAND
    53
    4E 4BL_0x4E_S_FETCH_OFFSET_6BL_CF
    4F 4BL_0x4F_S_VERIFY_OFFSET_6BL_CF
    56
    50 4BL_0x50_S_LOAD_UPDATE_1
    52 4BL_0x52_S_BRANCH
    59 HV_0x59_S_INIT_SOC_MMIO
    5A HV_0x5A_E_INIT_XEX_TRAINING
    5B HV_0x5B_E_INIT_KEYRING
    5C HV_0x5C_E_INIT_KEYS
    5F HV_0x5F_E_INIT_SOC_INT_COMPLETE
    60 KE_S_0x60_INIT_KERNEL
    61 KE_S_0x61_INIT_HAL_PHASE_0
    63 KE_S_0x63_INIT_KERNEL_DEBUGGER
    64 KE_S_0x64_INIT_MEMORY_MANAGER
    65 KE_S_0x65_INIT_STACKS
    66 KE_S_0x66_INIT_OBJECT_SYSTEM
    67 KE_S_0x67_INIT_PHASE1_THREAD
    68 KE_S_0x68_INIT_PROCESSORS
    69 KE_S_0x69_INIT_KEY_VAULT
    6A KE_S_0x6A_INIT_HAL_PHASE_1
    6B KE_S_0x6B_INIT_SFC_DRIVER
    6C KE_S_0x6C_INIT_SECURITY
    6D KE_S_0x6D_INIT_KEY_EX_VAULT
    6E KE_S_0x6E_INIT_SETTINGS
    6F KE_S_0x6F_INIT_POWER_MODE



    Ora provo a creare una nand originale



    Per quanto riguarda la sequenza dei post code che ho messo aprendo sto topic,probabilmente mancano tutti i postcode dopo l'1BL in quanto era una nand originale con CB 5773 e se ricordo bene nn ha i post code,mi e' venuto in mente poco fa xD
    Ultima modifica di marchisio80; 15-10-2015 alle 22:27

  8. #6
    Moderatore L'avatar di DrSchottky
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    Pi che i postcode mancanti l'ordine che sballato. Le retail se non sbaglio non hanno i post sui BL, ma sul Kernel dovrebbero esserci comunque.
    FB non ti parte perch si inchioda sul post 0x6F. Prova a far pressione su SB/GPU, magari da reballare.

  9. Thanks marchisio80 Ha ringraziato per questo post
  10. #7
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    Piccolo aggiornamento



    -nand originale,anche se ricreata,sempre uguale

    hex description

    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    10
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE
    13 1BL_0x13_S_FSB_CONFIG_TX_STATE
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    16 1BL_0x16_S_FETCH_HEADER
    17 1BL_0x17_S_VERIFY_HEADER
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1A 1BL_0x1A_S_RC4_INITIALIZE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1E 1BL_0x1E_S_BRANCH
    59 HV_0x59_S_INIT_SOC_MMIO
    FF HV_0xFF_E_FATAL
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE
    13 1BL_0x13_S_FSB_CONFIG_TX_STATE
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    16 1BL_0x16_S_FETCH_HEADER
    17 1BL_0x17_S_VERIFY_HEADER
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1A 1BL_0x1A_S_RC4_INITIALIZE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1F
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1E 1BL_0x1E_S_BRANCH
    59 HV_0x59_S_INIT_SOC_MMIO
    FF HV_0xFF_E_FATAL
    0
    10
    11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
    12 1BL_0x12_S_FSB_CONFIG_RX_STATE
    13 1BL_0x13_S_FSB_CONFIG_TX_STATE
    14 1BL_0x14_S_FSB_CONFIG_TX_CREDITS
    15 1BL_0x15_S_FETCH_OFFSET
    16 1BL_0x16_S_FETCH_HEADER
    17 1BL_0x17_S_VERIFY_HEADER
    18 1BL_0x18_S_FETCH_CONTENTS
    19 1BL_0x19_S_HMACSHA_COMPUTE
    1A 1BL_0x1A_S_RC4_INITIALIZE
    1B 1BL_0x1B_S_RC4_DECRYPT
    1C 1BL_0x1C_S_SHA_COMPUTE
    1D 1BL_0x1D_S_SIG_VERIFY
    1E 1BL_0x1E_S_BRANCH
    59 HV_0x59_S_INIT_SOC_MMIO
    FF HV_0xFF_E_FATAL
    0




    sta console era stata in assistenza ma nn so che aveva,tornata con CB 5772
    dopo un po' E64
    e' stata aggiornata anni fa e nn mi ricordo se dava sempre e64
    ora fa cosi


    ho giocato un po' di ore con gli emulatori e nn ha dato problemi
    Ultima modifica di marchisio80; 16-10-2015 alle 06:15

  11. #8
    Moderatore L'avatar di DrSchottky
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    Schianta sull'HyperVisor: con Freeboot probabilmente grazie a qualche patch riesce a fare qualche altro passo, ma non arriva comunque alla fine.
    Io dico HW azzoppato. Hai provato a far pressione?
    marchisio80 likes this.

  12. #9
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    Gia',dev'essere proprio come dici tu

    nand originale,qualsiasi kernel,si pianta sempre allo stesso punto

    [S]nand freeboot,si pianta in punti diversi dell'HyperVisor,ogni kernel in un punto preciso,che cambia al variare del kernel[/S]



    pressione si,ho provato,ma nn sembra sortire effetti

    faro' ancora qualche prova,sta console mi interessava solo perche' era una E64 e vedendo le nuove "Guide" che hai scritto e stai scrivendo,volevo provare qui in forum ad aggiornarmi la patch x i nuovi kernel

    errore mio a nn controllare prima di scrivere nuova nand se la console si avviava e dava ancora E64
    Ultima modifica di marchisio80; 16-10-2015 alle 22:32

  13. #10
    Moderatore L'avatar di DrSchottky
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    Con Freeboot si pianta sul kernel o sull'HV?
    A quali post?

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