0
1B 1BL_0x1B_S_RC4_DECRYPT
11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
12 1BL_0x12_S_FSB_CONFIG_RX_STATE
13 1BL_0x13_S_FSB_CONFIG_TX_STATE
15 1BL_0x15_S_FETCH_OFFSET
16 1BL_0x16_S_FETCH_HEADER
17 1BL_0x17_S_VERIFY_HEADER
18 1BL_0x18_S_FETCH_CONTENTS
19 1BL_0x19_S_HMACSHA_COMPUTE
1A 1BL_0x1A_S_RC4_INITIALIZE
1B 1BL_0x1B_S_RC4_DECRYPT
1C 1BL_0x1C_S_SHA_COMPUTE
1D 1BL_0x1D_S_SIG_VERIFY
1E 1BL_0x1E_S_BRANCH
D0 2BLL_0xD0_S_BEGIN
D1 2BLL_0xD1_S_READ_FUSES
D3 2BLL_0xD3_S_FETCH_HEADER_CB_B
D4 2BLL_0xD4_S_VERIFY_HEADER_CB_B
D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
D6 2BLL_0xD6_S_HMACSHA_COMPUTE_CB_B
D7 2BLL_0xD7_S_RC4_INITIALIZE_CB_B
DF
D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
DA 2BLL_0xDA_S_SHA_VERIFY_CB_B
FA
F2 2BLL_0xF2_E_SHA_VERIFY_CB_B
0
10
11 1BL_0x11_S_FSB_CONFIG_PHY_CONTROL
12 1BL_0x12_S_FSB_CONFIG_RX_STATE
13 1BL_0x13_S_FSB_CONFIG_TX_STATE
15 1BL_0x15_S_FETCH_OFFSET
16 1BL_0x16_S_FETCH_HEADER
17 1BL_0x17_S_VERIFY_HEADER
18 1BL_0x18_S_FETCH_CONTENTS
19 1BL_0x19_S_HMACSHA_COMPUTE
1A 1BL_0x1A_S_RC4_INITIALIZE
1B 1BL_0x1B_S_RC4_DECRYPT
1C 1BL_0x1C_S_SHA_COMPUTE
1D 1BL_0x1D_S_SIG_VERIFY
1E 1BL_0x1E_S_BRANCH
D0 2BLL_0xD0_S_BEGIN
D1 2BLL_0xD1_S_READ_FUSES
D3 2BLL_0xD3_S_FETCH_HEADER_CB_B
D7 2BLL_0xD7_S_RC4_INITIALIZE_CB_B
D5 2BLL_0xD5_S_FETCH_CONTENTS_CB_B
D6 2BLL_0xD6_S_HMACSHA_COMPUTE_CB_B
D7 2BLL_0xD7_S_RC4_INITIALIZE_CB_B
D8 2BLL_0xD8_S_RC4_DECRYPT_CB_B
D9 2BLL_0xD9_S_SHA_COMPUTE_CB_B
DA 2BLL_0xDA_S_SHA_VERIFY_CB_B
DB 2BLL_0xDB_S_BRANCH_CB_B
20 2BL_0x20_S_BEGIN
21 2BL_0x21_S_INIT_SECOTP
22 2BL_0x22_S_INIT_SECENG
2F 2BL_0x2F_S_RELOCATE
2E 2BL_0x2E_S_HWINIT
31 2BL_0x31_S_FETCH_HEADER_4BL_CD
33 2BL_0x33_S_FETCH_CONTENTS_4BL_CD
34 2BL_0x34_S_HMACSHA_COMPUTE_4BL_CD
35 2BL_0x35_S_RC4_INITIALIZE_4BL_CD
37 2BL_0x37_S_SHA_COMPUTE_4BL_CD
36 2BL_0x36_S_RC4_DECRYPT_4BL_CD
37 2BL_0x37_S_SHA_COMPUTE_4BL_CD
3B 2BL_0x3B_S_PCI_INIT
3A 2BL_0x3A_S_BRANCH
40 4BL_0x40_S_BEGIN
42 4BL_0x42_S_FETCH_HEADER
44 4BL_0x44_S_FETCH_CONTENTS
45 4BL_0x45_S_HMACSHA_COMPUTE
46 4BL_0x46_S_RC4_INITIALIZE
47 4BL_0x47_S_RC4_DECRYPT
4F 4BL_0x4F_S_VERIFY_OFFSET_6BL_CF
48 4BL_0x48_S_SHA_COMPUTE
4B 4BL_0x4B_S_LZX_EXPAND
53
4E 4BL_0x4E_S_FETCH_OFFSET_6BL_CF
4F 4BL_0x4F_S_VERIFY_OFFSET_6BL_CF
50 4BL_0x50_S_LOAD_UPDATE_1
52 4BL_0x52_S_BRANCH
59 HV_0x59_S_INIT_SOC_MMIO
5A HV_0x5A_E_INIT_XEX_TRAINING
5B HV_0x5B_E_INIT_KEYRING
5F HV_0x5F_E_INIT_SOC_INT_COMPLETE
5C HV_0x5C_E_INIT_KEYS
5F HV_0x5F_E_INIT_SOC_INT_COMPLETE
61 KE_S_0x61_INIT_HAL_PHASE_0
63 KE_S_0x63_INIT_KERNEL_DEBUGGER
64 KE_S_0x64_INIT_MEMORY_MANAGER
65 KE_S_0x65_INIT_STACKS
66 KE_S_0x66_INIT_OBJECT_SYSTEM
67 KE_S_0x67_INIT_PHASE1_THREAD
68 KE_S_0x68_INIT_PROCESSORS
69 KE_S_0x69_INIT_KEY_VAULT
6A KE_S_0x6A_INIT_HAL_PHASE_1
6B KE_S_0x6B_INIT_SFC_DRIVER
6C KE_S_0x6C_INIT_SECURITY
6D KE_S_0x6D_INIT_KEY_EX_VAULT
6E KE_S_0x6E_INIT_SETTINGS
6F KE_S_0x6F_INIT_POWER_MODE
70 KE_S_0x70_INIT_VIDEO_DRIVER
0