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About LinkBacksPiù che sfiga, con quella MFR Date sarebbe stato un miracolo il contrario.Originariamente Scritto da peppep
Più che sfiga, con quella MFR Date sarebbe stato un miracolo il contrario.
Ormai girano solo queste ....già da un bel po'
Sono ottimista a riguardo
Ho letto....anche su forum stranieri...a dire il vero...che ci stai lavorando...sei grande
No, purtroppo non ci sto lavorando(non l'ho mai fatto concretamente e non conto di farlo a breve).
Qualche idea ce l'ho, ma al momento sono occupato con altro.
Dr.Quake suggested to use the end of CB_B reading from NAND as reference point - we have nothing else closer to the check.
PetrozPL's suggestion was to add into SMC code signal output right after finishing NAND data exchange, but I think, CE line may be enough.
To make the CPU more reliable on such long time frames, my idea was to apply slowdown only right before glitch, and this way we must use HANA (dynamic) ref CLK for counting - like Stone chip.
Dr.Schottky, you did amazing research into X360 reversing and pretty skilled now
What do you think?
Hi 15432, wait DR.Schottky reply, but for me CE can be a reliable way.
I'm not sure, but the idea is Southbridge enables NAND only for the reading, so when CE rises, Southbridge finishes data exchange.
that must be checked... Maybe it's always enabled after booting.
ok, checked on Xenon - CE is almost always UP, so SB really enables NAND only for data exchange
Ultima modifica di 15432; 07-11-2015 alle 13:04
I tested CB_B loading from NAND last spring.
Meh.
so what the result you got?
the whole NAND reading isn't reliable reference point (low frequency, delays, etc) - the idea is to catch when SB tells CPU read is finished.
Since that, execution must be pretty determined.
Of course 4 seconds of RSA calculations aren't reliable under slowdown, but what about not slowed CPU?
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